A 3D chip with carbon nanotube transistors
A group of researchers at Stanford University managed to use carbon nanotubes to create a monolithic integrated circuit with memory and logic elements arranged in stacks. In the course of 2013, a group of researchers at Stanford was able to realize the first conceptual prototype processor based on carbon nanotubes. We speak of the conceptual prototype because with a speed of just 1 kilohertz and with fewer transistors 200, there was no possibility to compete with traditional processor’s silicon that we employ in our daily PC.
The gap between silicon and carbon nanotubes could start to decline: last December at IEDM – International Electron Devices Meeting – the same team has recently shown the possibility of realizing transistors based on carbon nanotubes much more performance and able, at least potentially, to get to compete with silicon transistors of similar dimensions. H.-S. Philip Wong, coordinator of the research team, said: ” Now that we have these nanotubes that are at par with the silicon, we can think of building high performance systems. ” The researchers claim to be able to realize transistors of carbon nanotubes directly on silicon.
Carbon nanotubes, in contrast to graphene, can be natural semiconductors and already for some time are considered as a potential material for switches to achieve high efficiency. In practice has proven rather complicated the realization of transistors with a sufficient number of carbon nanotubes such as to ensure the correct amount of current. With the current techniques for production of carbon nanotubes, there is a tendency to obtain a material that has some disadvantages in terms of purity – with the presence of metal elements – and homogeneity.
The previous work on carbon nanotubes has enabled researchers to Stanford to have a starting point from which to optimize the process of realization of the carbon nanotubes, which is now being conducted on a quartz substrate. Once grown nanotubes is applied on their top a layer of gold and finally a thermal tape that allows to remove the nanotubes from the quartz substrate and transferring the reference surface. The heat tape is removed and the dissolved gold by means of a special chemical bath.
This process provides a yield of about 8 nanotubes per micrometer, measured perpendicular to the direction of the electric current. The team has shown the possibility of repeating the deposition process for several times, using a particular polymer that prevents the risk that nanotubes sticking together to form a coil when they are exposed to the liquid used for the removal of gold, and that makes the surface of the nanotubes more homogeneous in preparation for the next deposition. In this way, it was possible to realize transistors with an average density of 100 nanotubes per micrometer and with a current density of 122 microamperes per micrometer.
This is not a record: already in 2013 a team of Thomas Watson Research Center of IBM has documented a density of more than 500 carbon nanotubes per micrometer in an oily suspension. In experiments conducted by researchers at IBM, There are nanotubes characterized by metallic impurities, which could have affected the on / off ratio, bringing it to 600: 1. The goal of researchers at Stanford is a ratio of 6000: 1, which describes a situation in which only a minimal amount of current is dispersed from the device even when turned off. By way of comparison in a normal transistor made with the usual technique’s CMOS you search for a on / off ratio of about 10,000: 1.
To test the compatibility with the silicon, the Stanford team used a strategy of multiple transfers to create a three-dimensional monolithic integrated circuit. A monolithic circuit is composed of a single ” thrown ” of material on a single silicon substrate, building up layers on one another connected by thick metal interconnections. Researchers have been able to build a crossbar switch, a circuit that can be used to connect different inputs and outputs, by a single silicon layer, two layers of resistive RAM and a layer of carbon nanotube transistors. The stack was made without exceeding the temperature of 400° C, which else it would have led to damage of the transistor.
It is the first time that it was possible to observe memory and logic circuitry stacked together in a monolithic. This combination could significantly reduce the time and energy required to move the information within a computer. Bring chips made from carbon nanotubes in volume production could be an even distant in time: the transport channels in transistors based on carbon nanotubes have a length of 400 nanometers, 10 times the size of the cutting-edge devices. So you need to find a way to make transistors smaller circuits for higher density.
The next step is therefore represented by the realization of transistors with shorter channels. This is a viable route: previously a series of research activities IBM have demonstrated the possibility to realize transistors nanotube with a channel length of from about 10 nanometers. Wong argues that there are still a number of obstacles that still need to be overcome before we can think about the commercial realization of high-performance circuits: the first are the metal contacts that connect to the nanotubes, as happens in the contacts of other devices, see grow the electrical resistance with the reduction in size. ” Having a technology that can compete with silicon, at least in the academic world, it would be tremendously exciting, ” said Wong.
